Hi Elkers,
this has been asked 5 years ago already.
Would you be so kind to release the source code for the Coolrunner II CPLD that is featured on your board that you no longer support?
I paid a lot of money for the Elk-Pi hat and the Blackboard and I do not want to throw those beautifully designed boards into the trash.
I figured out most of the things you have done by looking at the schematics and the source code of your drivers.
I also can guess that the CPLD should be turning the TDM LRCLK (high for 128 BCLK cycles, low for another 128 BCLK cyles) into a 24 bit left justified LRCLK, switching from high to low every 32 BCLK cycles.
Three days ago I didn’t even know what JTAG boundary scans are really about, but I managed to solder some pins to the Elk Pi Hat board, connect my Segger JLink Edu Mini to it with some Dupont cables and an adapter, download OpenOCD and the XC2C64A_VQ44.bsdl, learn some Tcl again (I thought this programming language was dead since the late 90s), and write some test code.
The test code starts by pulling up pin 29 high and then low again, which you seem to be doing in your driver too as some kind of reset.
The test code the continues with LRCLK high, toggles BCLK every step and after 256 steps (== 128 BCLK cycles) turns LRCLK low.
The test code only worked once correctly, showing that bit 115 of the BSR (which is IO_41, OUTPUT3 == pin 22 == LROUT in the Elk Pi schematics), was toggled after every 32 BCLKs,
I have problems to reproduce this behavior. Most of the times I don’t see any changes, sometimes I see toggling of LROUT kick in very late. I have no idea why.
So, could you please make the CPLD source code available, so that I could see what you’re really doing with this chip and properly flash it again in case I really f*ck things up?